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Senin, 26 September 2011
Minggu, 27 Juni 2010
FO4
Fan out = Cload / Cin
Cload = total MOS gate capacitance driven by the logic gate under consideration
Cin = the MOS gate capacitance of the logic gate under consideration
As a delay metric, one FO4 is the delay of an inverter, driven by an inverter 4x smaller than itself, and driving an inverter 4x larger than itself. Both conditions are necessary since input signal rise/fall time affects the delay as well as output loading.
A fan out of 4 is the answer to the canonical problem stated as follows: Given a fixed size inverter, small in comparison to a fixed large load, minimize the delay in driving the large load. After some math, it can be shown that the minimum delay is achieved when the load is driven by a chain of N inverters, each successive inverter ~4x larger than the previous; N ~ log4(Cload/Cin).
Interestingly, in the absence of parasitic capacitances (drain diffusion capacitance and wire capacitance), the result is "a fan out of e" (now N ~ ln(Cload/Cin).
If the load itself is not large, then using a fan out of 4 scaling in successive logic stages does not make sense. In these cases, minimum sized transistors may be faster.
Because scaled technologies are inherently faster (in absolute terms), circuit performance can be more fairly compared using the fan out of 4 as a metric. For example, given two 64-bit adders, one implemented in a 0.5um technology and the other in 90nm technology, it would be unfair to say the 90nm adder is better from a circuits and architecture standpoint just because it has less latency. The 90nm adder might be faster only due to its inherently faster devices. To compare the adder architecture and circuit design, it is more fair to normalize each adder's latency to the delay of one FO4 inverter.
http://en.wikipedia.org/wiki/FO4
Cload = total MOS gate capacitance driven by the logic gate under consideration
Cin = the MOS gate capacitance of the logic gate under consideration
As a delay metric, one FO4 is the delay of an inverter, driven by an inverter 4x smaller than itself, and driving an inverter 4x larger than itself. Both conditions are necessary since input signal rise/fall time affects the delay as well as output loading.
A fan out of 4 is the answer to the canonical problem stated as follows: Given a fixed size inverter, small in comparison to a fixed large load, minimize the delay in driving the large load. After some math, it can be shown that the minimum delay is achieved when the load is driven by a chain of N inverters, each successive inverter ~4x larger than the previous; N ~ log4(Cload/Cin).
Interestingly, in the absence of parasitic capacitances (drain diffusion capacitance and wire capacitance), the result is "a fan out of e" (now N ~ ln(Cload/Cin).
If the load itself is not large, then using a fan out of 4 scaling in successive logic stages does not make sense. In these cases, minimum sized transistors may be faster.
Because scaled technologies are inherently faster (in absolute terms), circuit performance can be more fairly compared using the fan out of 4 as a metric. For example, given two 64-bit adders, one implemented in a 0.5um technology and the other in 90nm technology, it would be unfair to say the 90nm adder is better from a circuits and architecture standpoint just because it has less latency. The 90nm adder might be faster only due to its inherently faster devices. To compare the adder architecture and circuit design, it is more fair to normalize each adder's latency to the delay of one FO4 inverter.
http://en.wikipedia.org/wiki/FO4
Jumat, 25 Juni 2010
Electronics Project Design References and Tips
Good Electronics Project Design References and Tips Can Accelerate Your Practical Know-How in Electronics.
Getting good and timely information on the electronics project that you are embarking on sometimes can be time consuming and frustrating. Hence, the objective of this site is to bridge this gap. This site is dedicated to all electronics enthusiasts whether you are a student, a teacher, hobbyist or even an electronics engineer.
The end result of an electronics project is determined by a few factors. It normally starts with the strong enthusiasm in the project chosen, going on to schematic or circuit design, printed circuit board design, software programming if microcontroller is involved and building protoypes.
This site provides schematics and parts lists of various projects that you can experiment yourself. It also include articles on the importance of reliability testing, electromagnetic compatibility (EMC) testing, failure mode effect and Analysis (FMEA), fundamental of electronic parts and test/measurement tools that are needed before you embark on your journey of building your own electronics project.
This Electroncs Project Design site will be updated from time to time with new articles and tips, so remember to check back here occasionally.
If you find this site useful and would like to contribute ideas to be included in this site, you are most welcome to email the author. Your comment on the contents of this Electronics Project Design site is most welcome.
http://www.electronics-project-design.com/
Getting good and timely information on the electronics project that you are embarking on sometimes can be time consuming and frustrating. Hence, the objective of this site is to bridge this gap. This site is dedicated to all electronics enthusiasts whether you are a student, a teacher, hobbyist or even an electronics engineer.
The end result of an electronics project is determined by a few factors. It normally starts with the strong enthusiasm in the project chosen, going on to schematic or circuit design, printed circuit board design, software programming if microcontroller is involved and building protoypes.
This site provides schematics and parts lists of various projects that you can experiment yourself. It also include articles on the importance of reliability testing, electromagnetic compatibility (EMC) testing, failure mode effect and Analysis (FMEA), fundamental of electronic parts and test/measurement tools that are needed before you embark on your journey of building your own electronics project.
This Electroncs Project Design site will be updated from time to time with new articles and tips, so remember to check back here occasionally.
If you find this site useful and would like to contribute ideas to be included in this site, you are most welcome to email the author. Your comment on the contents of this Electronics Project Design site is most welcome.
http://www.electronics-project-design.com/
Rabu, 23 Juni 2010
Medical Devices Get Ready To Make House Calls
The population is aging and medical costs are soaring, creating a greater need for home-based healthcare solutions. These pressures have led to an increase in the number of healthcare devices on the market as smaller, portable, and less expensive homecare technologies replace larger, costlier equipment.
The numbers are daunting. According to the World Health Organization (WHO), the worldwide number of people age 50 and older was 650 million in 2006. WHO expects this total to reach 1.2 billion by 2025. In the U.S. alone, those age 65 or older now constitute an increasing share of the population, a number that is expected to rise steadily in the future.
The healthcare market is big business. According to the U.S. government, the U.S. spends $2.5 trillion on healthcare, representing 18% of the nation’s gross domestic product (GDP). ABI Research forecasts that 59 million wearable home health devices will be used by 2014 and that the total number of wearable devices will be 420 million by then, when devices for sports and fitness applications are counted.
The Freedonia Group puts the present market value of home healthcare medical equipment at well over $7 billion, when technologies for respiratory therapy, intravenous (IV) injections, dialysis, patient monitoring, wheelchairs, walking assistance, medical furniture, and safety devices are considered.
Today’s devices give patients a lower-cost and hassle-free option for monitoring and in some cases treating their health conditions right in their own homes. There’s less of a need to have them travel to a hospital, medical clinic, or doctor’s office. Healthcare is becoming more decentralized.
Portable home healthcare medical gadgets include blood glucose, blood pressure, and heart rate monitors, digital thermometers, pulse oximeters, wheezometers for patients with asthma and other respiratory disorders, fall and movement detection devices for the elderly and disabled, and digital scales for weight monitoring and management. Therapeutic devices for sleep apnea are available as well. And, many home fitness devices are being updated to include health measurement and management functions
http://electronicdesign.com/article/cover-story/medical_devices_get_ready_to_make_house_calls.aspx
The numbers are daunting. According to the World Health Organization (WHO), the worldwide number of people age 50 and older was 650 million in 2006. WHO expects this total to reach 1.2 billion by 2025. In the U.S. alone, those age 65 or older now constitute an increasing share of the population, a number that is expected to rise steadily in the future.
The healthcare market is big business. According to the U.S. government, the U.S. spends $2.5 trillion on healthcare, representing 18% of the nation’s gross domestic product (GDP). ABI Research forecasts that 59 million wearable home health devices will be used by 2014 and that the total number of wearable devices will be 420 million by then, when devices for sports and fitness applications are counted.
The Freedonia Group puts the present market value of home healthcare medical equipment at well over $7 billion, when technologies for respiratory therapy, intravenous (IV) injections, dialysis, patient monitoring, wheelchairs, walking assistance, medical furniture, and safety devices are considered.
Today’s devices give patients a lower-cost and hassle-free option for monitoring and in some cases treating their health conditions right in their own homes. There’s less of a need to have them travel to a hospital, medical clinic, or doctor’s office. Healthcare is becoming more decentralized.
Portable home healthcare medical gadgets include blood glucose, blood pressure, and heart rate monitors, digital thermometers, pulse oximeters, wheezometers for patients with asthma and other respiratory disorders, fall and movement detection devices for the elderly and disabled, and digital scales for weight monitoring and management. Therapeutic devices for sleep apnea are available as well. And, many home fitness devices are being updated to include health measurement and management functions
http://electronicdesign.com/article/cover-story/medical_devices_get_ready_to_make_house_calls.aspx
Selasa, 22 Juni 2010
Very Low-Power Inrush-Current Limiter Protects Hot-Pluggable Apps
Inrush current occurs in many circuits that are hot-plugged into a power supply or battery, causing the input load capacitor to experience a sudden surge of current. This surge can damage or degrade the input capacitor, generate a damaging spark upon initial contact, cause a voltage droop that can adversely affect other circuits, trip a line fuse, and generate unwanted electromagnetic interference.
Designers can use thermistors to limit inrush current. But the presence of a series resistance, the required cool-down period, or the package size may not be suitable for some circuits. Hot-swap controllers and MOSFET drivers are another choice. However, their input voltage range may be limited and they usually draw more than several hundred microamps of quiescent current, which is too much for low-power applications.
The circuit in Figure 1 uses a high-side PMOS transistor to implement a simple, extremely low-power inrush current limiter with a wide input-voltage range. It presents a high-impedance load to the supply voltage (VSupply), which eliminates sparking upon initial contact. When VSupply is applied, the PMOS is slowly switched on. This eliminates a droop in VSupply and slowly ramps the input voltage (VIn) across the load’s input capacitance (CIn) to minimize the inrush current (ICIN). Due to M5’s input capacitance, its gate is initially low when VSupply is applied. But it rapidly pulls up via M7, which remains on for a period of time (adjustable by C1) longer than it takes for M5’s gate to fully charge and turn off. During this time, some amount of current passes through M5.
Designers must carefully consider the tradeoff between M5’s gate charge and RDS(ON). Yet the amount of pass-through current plus gate-charge current will be several orders of magnitude less than the inrush current without the limiter.
Simultaneously, when VSupply is applied, the cascode current mirror formed by M1-M4 begins to sink ISink amps to ground. Zener diode D1 and R1 provide a constant voltage for the current mirror, and R2 sets ISink by:
Since VDS cannot be analytically calculated from datasheet information, Spice tools or prototyping is required. Fortunately, the current mirror can use a variety of NMOS transistors.
In MOSFET data sheets, the portion of the plot of total gate charge (QG) versus gate-to-source voltage (VGS) where VGS is held constant is called the Miller Plateau. In this region, the drain-to-source voltage (VDS) changes linearly, virtually independent of the drain current.
Therefore, removing charge linearly within this region, as is done by ISink (once M7 is turned off) will ensure a linear change in VDS, causing dVIn/dt to be constant. Assuming VIn = VSupply when M5 is fully enhanced, ICIN is approximately:
where:
Here, ΔT is the VIn ramp up time, and ΔQ is the charge difference between the beginning and the end of the Miller Plateau obtained from the M5 datasheet, which can be used to calculate ΔT within a factor of 2 to 3 from the actual performance.
D2 clamps VGS(M5) = –VZener(D2), keeping it below the maximum allowed for M5. R4 isolates M2 and M4 from VSupply, reducing the total intrinsic capacitance seen by the supply voltage. Driving the gate of M6 high will rapidly deactivate M5, isolating the load from VSupply. Driving it low will once again ramp up VIn.
The choice of transistors allows a wide VSupply range. The use of logic-level transistors for M1-M7 governs VSupply(min), and a high reverse breakdown voltage (VDSS) for M2, M5, and M6 governs VSupply(max). The transistors used allow a VSupply of 3 V to 30 V. At 30 V, the maximum steady-state current consumption is less than 1.5 µA (and less than 1 µA at 20 V). The bulk of that current provides the regulated voltage for the current mirror.
Figure 2 shows an alternative current sink. The rail-to-rail op amp forces VRef, which is set by R1 and R2, to appear across R4 to set ISink, in this case 200 nA. For low-voltage operations, M1 must be a logic-level NMOS. For high-voltage operations, VDSS(M1) must be greater than VSupply. A low-power linear regulator (LT3008) provides the supply voltage for the op amp. This current sink typically draws about 10 µA, but it has the advantage of relying only on VRef and R4 to set ISink.
http://electronicdesign.com/article/ideas-for-design/very_low_power_inrush_current_limiter_protects_hot_pluggable_apps.aspx
Designers can use thermistors to limit inrush current. But the presence of a series resistance, the required cool-down period, or the package size may not be suitable for some circuits. Hot-swap controllers and MOSFET drivers are another choice. However, their input voltage range may be limited and they usually draw more than several hundred microamps of quiescent current, which is too much for low-power applications.
The circuit in Figure 1 uses a high-side PMOS transistor to implement a simple, extremely low-power inrush current limiter with a wide input-voltage range. It presents a high-impedance load to the supply voltage (VSupply), which eliminates sparking upon initial contact. When VSupply is applied, the PMOS is slowly switched on. This eliminates a droop in VSupply and slowly ramps the input voltage (VIn) across the load’s input capacitance (CIn) to minimize the inrush current (ICIN). Due to M5’s input capacitance, its gate is initially low when VSupply is applied. But it rapidly pulls up via M7, which remains on for a period of time (adjustable by C1) longer than it takes for M5’s gate to fully charge and turn off. During this time, some amount of current passes through M5.
Designers must carefully consider the tradeoff between M5’s gate charge and RDS(ON). Yet the amount of pass-through current plus gate-charge current will be several orders of magnitude less than the inrush current without the limiter.
Simultaneously, when VSupply is applied, the cascode current mirror formed by M1-M4 begins to sink ISink amps to ground. Zener diode D1 and R1 provide a constant voltage for the current mirror, and R2 sets ISink by:
Since VDS cannot be analytically calculated from datasheet information, Spice tools or prototyping is required. Fortunately, the current mirror can use a variety of NMOS transistors.
In MOSFET data sheets, the portion of the plot of total gate charge (QG) versus gate-to-source voltage (VGS) where VGS is held constant is called the Miller Plateau. In this region, the drain-to-source voltage (VDS) changes linearly, virtually independent of the drain current.
Therefore, removing charge linearly within this region, as is done by ISink (once M7 is turned off) will ensure a linear change in VDS, causing dVIn/dt to be constant. Assuming VIn = VSupply when M5 is fully enhanced, ICIN is approximately:
where:
Here, ΔT is the VIn ramp up time, and ΔQ is the charge difference between the beginning and the end of the Miller Plateau obtained from the M5 datasheet, which can be used to calculate ΔT within a factor of 2 to 3 from the actual performance.
D2 clamps VGS(M5) = –VZener(D2), keeping it below the maximum allowed for M5. R4 isolates M2 and M4 from VSupply, reducing the total intrinsic capacitance seen by the supply voltage. Driving the gate of M6 high will rapidly deactivate M5, isolating the load from VSupply. Driving it low will once again ramp up VIn.
The choice of transistors allows a wide VSupply range. The use of logic-level transistors for M1-M7 governs VSupply(min), and a high reverse breakdown voltage (VDSS) for M2, M5, and M6 governs VSupply(max). The transistors used allow a VSupply of 3 V to 30 V. At 30 V, the maximum steady-state current consumption is less than 1.5 µA (and less than 1 µA at 20 V). The bulk of that current provides the regulated voltage for the current mirror.
Figure 2 shows an alternative current sink. The rail-to-rail op amp forces VRef, which is set by R1 and R2, to appear across R4 to set ISink, in this case 200 nA. For low-voltage operations, M1 must be a logic-level NMOS. For high-voltage operations, VDSS(M1) must be greater than VSupply. A low-power linear regulator (LT3008) provides the supply voltage for the op amp. This current sink typically draws about 10 µA, but it has the advantage of relying only on VRef and R4 to set ISink.
http://electronicdesign.com/article/ideas-for-design/very_low_power_inrush_current_limiter_protects_hot_pluggable_apps.aspx
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